Method and apparatus for inspecting a semiconductor device

ABSTRACT

A method and its apparatus for inspecting a semiconductor device in which failure occurrence conditions on a whole wafer are estimated by calculating the statistic of potential contrasts in pattern sections from sampled images to implement higher throughout and defective conditions of process are detected at an early stage with the help of time series data of the estimated result.

BACKGROUND OF THE INVENTION

[0001] This invention relates to technology of inspecting asemiconductor device, more particularly, to a wafer inspection methodand its apparatus suitable for control of defective conditions of thefabricating processes in a semiconductor device production line.

[0002] In a semiconductor device, a conduction failure of contact holesleads to fatal defects including characteristic failures and has asignificant impact on yield of the semiconductor device. Such a failureis often caused by changes in production requirements or defectiveconditions of manufacturing equipment and often invites a large amountof defective units.

[0003] Such defective conditions of process are controlled, in general,by a means of periodically checking for changes in pattern geometrieswith a critical dimension measurement SEM. However, only evaluation ofpattern geometries cannot directly inspect conducting state of contactparts.

[0004] On the other hand, JP-A No. 2000-58608 etc. have disclosed Amethod of detecting conduction failures by using brightness of contactparts as well as pattern geometries. This method utilizes a feature ofan electron microscope image. Charge-up amount of a pattern byirradiation of electron beams varies depending on the conducting statesof contact parts and shows contrast between normal parts and defectiveparts on a secondary electron image to be detected. With such a methodas this, it is possible to inspect electrical characteristics thatcannot be checked by a visual check of the external view.

[0005] In recent years, wafer inspection apparatus using SEM images hasalso come to be utilized as has been disclosed in JP-A Nos. 1993-258703and 2000-208085 and efficient defect inspection has become possible.This kind of apparatus utilizes repeatability of the same patternscontaining devices such as cells and chips within the conductor tracesand compares images of these patterns to detect defects.

[0006] As stated above, a method using SEM images has come intowidespread usage as a means of detecting electrical conduction failuresof contact windows. However, it requires considerably long time toobtain an SEM image with a high signal-to-noise ratio and highresolution; it takes a few hours to tens of hours to perform inspectionof a whole wafer. Therefore, the in-line usage is difficult. Inaddition, an inspection method of performing comparison of images has adrawback in that, on the quantity occurrence of defects, images of thedefects are compared with each other, making an accurate defectinspection difficult.

[0007] In addition, all of these inspection methods are intended fordefect inspection, so they cannot predict occurrence of electricalconduction failures. However, since failures caused by changes inproduction requirements and defective conditions of manufacturingequipment can suddenly be encountered in a large amount and on a massivescale and invite too many wafers with defects at the same time of theoccurrence, it is desirable to detect changes in processes.

SUMMARY OF THE INVENTION

[0008] This invention provides A method of keeping track of failureoccurrence conditions on a whole wafer of interest by using as smellarea subject to an inspection as possible.

[0009] This invention also provides A method of controlling changes inprocesses to prevent a rash of failures caused by defective conditionsof manufacturing equipment.

[0010] In this invention, inspection is performed by obtaining chargedparticle beam images at a desired area on the surface of a wafer,calculating a typical signal amount value typifying the signal amount ofcharged particle beams emitted by each pattern from the obtained images,and estimating failure occurrence conditions outside the image-obtainedarea from the statistic of the typical signal amount value. In addition,this invention makes it easier to determine the causes of failures byproviding a function for displaying the time series data of inspectionresults for each equipment which treated the wafer.

[0011] In other words, this invention, in A method of inspecting a waferon the surface of which the same pattern is repetitively formed,comprises the steps of obtaining a charged particle beam image of adesired area of the wafer by detecting secondary charged particlesemitted from the surface of the wafer with irradiation of a focusedcharged particle beam onto the surface of the wafer, calculating theimage feature amount of each pattern within the desired area from theobtained charged particle beam images, computing the statistic of thecalculated image feature amount, comparing a preset value to thecomputed statistic of the image feature amount, and estimating thequality of patterns that have been formed outside the desired area fromthe result of the comparison.

[0012] In addition, this invention, in A method of inspecting a waferhaving patterns that have been repetitively formed on the surface of thewafer and have differences in geometries within a chip orinterconnecting conditions with a lower layer or in both, comprises thesteps of:

[0013] obtaining a charged particle beam image of a desired area of awafer,

[0014] calculating the image feature amount of each pattern contained inthe obtained charged particle beam image from the obtained chargedparticle beam image,

[0015] determining the statistic of the image feature amount computedfor each pattern type,

[0016] comparing a threshold that has been preset in association with apattern type to the statistic that has been computed for that patterntype, and

[0017] estimating the quality of patterns that have been formed outsidethe desired area from the result of the comparison.

[0018] Furthermore, this invention, in A method of inspecting a wafer onwhich a plurality of chips with the same pattern of traces are formed,comprises the steps of:

[0019] obtaining a charged particle beam image of a specific place onone of the plurality of chips by focusing charged particle beams ontothe specific place,

[0020] estimating the failure occurrence conditions of the remainingchips on the wafer with the help of inspection data obtained from thecharged particle beam image of the specific section,

[0021] determining the distribution of the estimated failure occurrenceconditions of the chips on the wafer, and

[0022] outputting information of the distribution of the failureoccurrence conditions on the wafer to be inspected.

[0023] This invention, in A method of manufacturing a semiconductordevice, comprises the steps of:

[0024] obtaining a charged particle beam image of a preset place byirradiating a focused charged particle beam onto the preset place on awafer that has been operated upon in given processing stages,

[0025] repeating this step for a plurality of wafers that have beenoperated upon in the given processing stages, and

[0026] comparing the brightness of the charged particle beam images ofthe specific places which have sequentially been obtained from theplurality of wafers with the preset values to control changes in processof the given processing stages.

[0027] This invention, in A method of manufacturing a semiconductordevice, comprises the steps of

[0028] determining the distribution of failures over a wafer from acharged particle beam image obtained by irradiating a focused chargedparticle beam onto a plurality of preset sections on a wafer that hasbeen operated upon in given processing stages, and

[0029] controlling changes in process of the given processing stages onthe basis of verifications in distribution of failures from wafer towafer.

[0030] This invention, in A method of manufacturing a semiconductordevice by processing it through a plurality of processing stages,excises the steps of:

[0031] obtaining a charged particle bean image of a preset section byirradiating a focused charged particle beam onto a preset place on agiven wafer after the given wafer has been operated upon in each of theplurality of processing stages, repeating the step for each of theplurality of processing stages, and

[0032] monitoring the brightness of the charged particle bean imagesobtained for each processing stage to control the plurality ofprocessing stages.

[0033] These and other objects, features and advantages of the inventionwill be apparent from the following more particular description ofpreferred embodiments of the invention, as illustrated in theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034]FIG. 1 is a plane view of a semiconductor device;

[0035]FIG. 2 is a plane view of a semiconductor device;

[0036]FIG. 3 is a plane view of masks used for exposure;

[0037]FIG. 4 is a process flow chart showing the processing stages of asemiconductor device;

[0038]FIG. 5 is a section view of a contact window pattern;

[0039]FIG. 6 (a) is a plane view of a wafer and chips;

[0040]FIG. 6 (b) is a drawing showing distribution of the brightness ofcontact window patterns;

[0041]FIG. 6 (c) is a drawing showing the relationship between thetypical brightness value and probability of the occurrences;

[0042]FIG. 7 is a drawing showing the relationship between contactresistance and signal amount;

[0043]FIG. 8 is a plane view of wafers showing failure occurrenceconditions varying with the time of commencement;

[0044]FIG. 9 shows section views of a wafer showing the offsetconditions against a lower pattern;

[0045]FIG. 10 shows section views of a wafer showing the offsetconditions against a lower pattern;

[0046]FIG. 11 is a plane view of a wafer showing inspection pointswithin a shot;

[0047]FIG. 12 (a) is a plane view of a chip showing a window pattern;

[0048]FIG. 12 (b) is a graph showing the relationship between thecoordinate data within the image and the brightness;

[0049]FIG. 12 (c) is a graph showing the relationship between thebrightness and the occurrence frequency;

[0050]FIG. 13 (a) is a plane view of a chip showing a contact windowpattern;

[0051]FIG. 13 (b) is a drawing showing the relationship betweencoordinates within the image and the brightness;

[0052]FIG. 13 (c) is a drawing showing the relationship between thebrightness and the occurrence frequency;

[0053]FIG. 14 (a) and FIG. 14 (b) are both plane views of semiconductorchips showing contact window patterns;

[0054]FIG. 15 (a) is a plane view of a semiconductor chip showing acontact window pattern;

[0055]FIG. 15 (b) is a drawing showing the relationship between thecoordinates within the image and the brightness;

[0056]FIG. 16 (a) is a plane view of a semiconductor chip showing thelayout of contact windows;

[0057]FIG. 16 (b) is a plane view of a semiconductor chip showing thecenter coordinates of each of the contact windows;

[0058]FIG. 16 (c) is a plane view of a semiconductor chip showing thestate of electron beam scanning on it;

[0059]FIG. 17 is a graph showing the relationship between etching timeand the brightness of a pattern;

[0060]FIG. 18 is a graph showing the relationship between the brightnessand the occurrence frequency;

[0061]FIG. 19 is a schematic plane view of the inspecting system showingan embodiment of the invention;

[0062]FIG. 20 is a schematic front view of an inspection system showinganother embodiment of the invention; and

[0063]FIG. 21 (a), FIG. 21 (b), and FIG. 21 (c) are drawings all showingthe relationship between the typical brightness values during inspectiontime and time and date of commencement.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0064]FIG. 1 shows an example of a logic unit of a semiconductor devicewhich is an object sample of the invention. This logic unit consists ofa unit cell 20 enclosed with a phantom line in a plane view shown inFIG. 1. The unit cell 20 consists of two pieces of n-channel MOS chip Q1and two pieces of p-channel NOS chip Q2. The n-channel MOS chip Q1 isformed on an n-type region 21 in the surface of a p-WELL region PWformed on a substrate, and the p-channel MOS chip Q2 is formed on ap-type region 22 in the surface of an n-WELL region NW, respectively.Here, a plane view of a unit cell before different types of traces 24A,24B, 24C, and 25 are formed on it is shown in FIG. 2. Reference numeral26 is a polysilicon gate pattern. This unit cell is structured in such away that 2-input NAND gates and 2-input NOR gate circuits can be formedefficiently by selecting traces to be subsequently added as necessary,and this structure is also extended to the structures connecting a largenumber of CMOS chips.

[0065]FIG. 3 shows example masks, which are used to form contact windowsand patterns of traces shown in FIG. 2, thereby making a circuit.

[0066] These semiconductor devices are fabricated by iteration of anumber of pattern-forming processes as shown in FIG. 4. Generally, eachpattern-forming process mainly consist of stages of oxidization 30,resist coating 31, exposure 32, developing 33, etching 34, resiststripping 35, and cleansing 36. Unless parameters of fabrication processat each of these stages are optimized, correct trace patterns of asemiconductor device cannot be formed, resulting in occurrence of failedproducts. These semiconductor devices are electrically analyzed afterthe completion of the wafer fabrication processes, causes of defects areexamined by fail-bit analysis and other methods, and a control againstthem is performed. However, with such a method, if failures haveoccurred somewhere in fabrication processes, they cannot be detecteduntil whole processing for the wafer of the product complete. It usuallytakes tens of days to manufacture a semiconductor device, so a methodlike this has a drawback in that defective units are produced in a largeamount before corrective action is taken.

[0067] In contrast to this, if visual checks 37, 38, and 39 areperformed in each stage of the fabricating processes as shown in FIG. 4,even for the occurrence of failures caused by defective conditions ofequipment, diagnosis and corrective action can be taken at an earlierstage. As a result of this, it becomes possible to reduce the number ofdefective units, improve production efficiencies, and increase profits.

[0068] Failures occurring in these fabricating processes includefailures occurring relatively on a random and local basis and failuresoccurring by defective conditions of fabricating equipment andfluctuations of process parameters. In particular, the latter type offailures might occur in an entire wafer or across several wafers and isprone to be produced in a large amount. It often has a remarkableoccurrence distribution.

[0069] This invention provides A method of controlling occurrence offailures to the minimum by detecting the latter type of failures at anearly stage, determining equipment causing the failures, and takingcorrective action. More specific examples of the latter type of failuresinclude resist residues caused by inadequate development and etching,and electrical conduction failures and short circuits caused by failedalignment with lower layer patterns. In addition, this inventionprovides A method of predicting occurrences of failures by controllingnormal levels.

[0070] As an example subject, FIG. 5 shows a section view of a contactwindow pattern where inadequate etching has occurred. Adequate etchingtime opens a contact widow 50 of a normal size as shown in FIG. 5 (a),but inadequate etching decreases a diameter of a window bottom 52 asshown in FIG. 5 (b), and with over a certain extent, resulting infailures causing high resistance. Further inadequate etching decreasesthe size of windows with oxide film residue 54 at some spots in thewindow bottom as shown in FIG. 5 (c), causing electrical conductionfailures. Lower etch uniformity of etching equipment causes variationsof the occurrence rate of such failures within the surface of a wafer.The presence or absence of these conditions can be determined by usingelectron microscope images.

[0071] When the surface of a specimen is scanned with electron beams,secondary electrons are emitted in response to the amount of electricalcharges on the surface. Since the amount of electrical charges of thesurface of a specimen depends on the electrical characteristics of apattern formed on the surface of the specimen, evaluating the signalamount of these secondary electrons enables determination of the qualityof the formed pattern. Hereinafter, an embodiment using electronmicroscope images will be described, but it is obvious that theapplication of other kinds of charged particle beam images such as SIM(secondary ion mass) images of FIB (focused ion beam) produces the sameeffect.

[0072] Referring to FIG. 6 and FIG. 7, a means for detecting electricalconduction failures of contact windows as shown in FIG. 5 will bedescribed. FIG. 6 shows an example of electrical conduction failurescaused by inadequate etching, which are gradually increasing toward thenotch side of a wafer 60. As shown in FIG. 6 (a), if a secondaryelectron beam image 62 obtained within a given group of chips 61 on thewafer 60 displays a normal section 63 of contact window patterns withhigh brightness and a failure section 64 of contact window patterns withlower brightness. Current inventions have proposed a method ofevaluating the quality of each contact window pattern on the basis ofthe variations of this brightness. With this method, especially when therelationship between signal amount of secondary electron beams detectedfrom the pattern of a contact window with an electron microscope andcontact resistance between the window part and an underlying conductoror thickness of a film residue is known as shown in FIG. 7, a thresholdlevel 68 for evaluating the quality of window patterns can easily bedetermined from the normal resistance value.

[0073] This invention enables estimation of failure occurrenceconditions in patterns of contact windows other than those the images ofwhich have been obtained. The brightness of contact window patternswithin images obtained for each chip is measured (FIG. 6 (b)). Where,the brightness of a window pattern is a typical value indicating thevariations of secondary electron amount emitted from the window pattern,such as an average brightness value and a maximum brightness valuewithin the window pattern area. If the average value and distribution ofbrightness of these window patterns are determined, probabilitydistribution functions 65, 66, and 67 on the assumption of normal(Gaussian) distribution can be determined as shown in FIG. 6 (c). Usingthe relationship between a result of this and a preset threshold levelfor evaluating the quality of patterns enables estimation of thepercentage of failed patterns in a chip from the representative image ofone of chips with same pattern. For example, in a chip B shown in FIG.6, although all windows within the detected image are normal, it can beestimated that there is 20 percent potential of failed window patternsexisting in other chips with the same pattern. If results of theseevaluations are displayed on a wafer map as shown in FIG. 6 (a), failureoccurrence conditions can easily be checked.

[0074] Current inventions have required quite a long time to detect thiskind of failure because they have to obtain electron beam images of anentire wafer before evaluating failures from the difference between thewindow pattern in an area of interest and window patterns outside thearea. In contrast to the method of the current inventions, the method ofthis invention enables estimation of the presence or absence of failureswith the help of smaller number of images of one or a few windows oneach chip, saving much inspection time and increasing the frequency ofsampling tests.

[0075] In the example in FIG. 6, failed contact window patterns havepractically been detected in chip C and chip D, but failure occurrencecan be estimated from the image of chip B. For example, in such a casethat the number of failures gradually increases with time ofcommencement from (a) to (b) and to (c) as shown in FIG. 8, keeping highsampling frequency makes it possible to detect defective conditions andtake corrective action during the impact of the failures on theproduction is small (before the state of FIG. 8 (b) or the previousstate).

[0076] In addition, such a method of current inventions as to detectcontrast differences between a pattern of an area of interest andpatterns outside the area cannot correctly detect failures if allpatterns have failures, while the method of the invention that evaluatesthe absolute values of the brightness of window patterns implementscorrect inspections even in such a case.

[0077]FIG. 6 shows a method of inspecting only a line of chips forsimplicity, but it would be possible to inspect all chips or optionallyfewer chips such as those at five positions (up, down, right and leftside and center positions). Of course, it would also be possible toincrease check positions within a chip. In order to evaluate variations,it is desirable that tens to hundreds of patterns (window patterns inthe case of FIG. 6) within a single image can be evaluated. If thesufficient number of patterns cannot be obtained in a single image,several images of other areas on the periphery of the area of interestmay be used to perform operations similar to these.

[0078] Note that the relationship between the brightness of a windowpattern and contact resistance between the window pattern and theunderlying conductor has to be determined for every inspection apparatusbecause it varies with acceleration voltages of electron beams orirradiation parameters such as bean current. A method of determining thecontrol values will be described later in detail.

[0079]FIG. 5 and FIG. 6 have shown examples of failures due toinadequate etching. Other failures such as offset against lower layerpatterns and alignment failure due to rotation and scaling at exposureas shown in FIG. 9 and FIG. 10 can also be detected. FIG. 9 shows anexample of increased contact resistance between a window pattern and theunderlying conductor caused by the alignment failure of a contact window80 on the first layer and a contact window 82 on the second layer. FIG.10 shows an example of a short circuit with conductor routing of thelower layer. In addition to inspection of failure distribution within awafer as shown in FIG. 8, performing a check of five positions (eachgiven reference numeral 88) including four corners and a center within ashot 87 as shown in FIG. 11 is preferable because it enables inspectionof alignment failures in a shot. In addition to inspections of thesewindow patterns, characteristics inspection can be performed similarlyfor whatever with the same pattern repeated, including patterns afterwindows are filled, resist patterns, and well patterns formed on thesubstrate.

[0080] Then, referring to FIG. 12 and FIG. 13, an example method ofmeasuring the typical brightness value of each widow using these imagesof patterns. In advance, the average brightness of a groundwork 90 and awindow pattern 91 are determined with the help of an image of an normalsection. For example, it may be determined at the peaks of a patternwaveform 94 of an image as shown in FIG. 12 (b) or with the use of ahistogram 95 as shown in FIG. 12 (c). A threshold level ThL for imageprocessing is determined from the measurement value of the brightness.The threshold level ThL is determined separately from the control valuefor evaluating the quality of patterns and is used for identifying thepositions of patterns and computing the typical brightness value.

[0081] First, as show in FIG. 13 (a), an image 62 of a section to beinspected is scanned sequentially from top left and searched for pointsover the threshold level ThH 100 to determine the positions of patterns.In FIG. 13, pattern B is detected first. As shown in FIG. 13 (b),starting form position 102 of pattern B, patterns in positions at adistance by repetition pitch p of a cell pattern are searched todetermine the positions of pattern A and pattern C. Next, the positionof pattern D is determined from the position of pattern C. In this way,all pixels within the image 62 are searched for in the X and Ydirections to determine positions of patterns within the image. Where,calculation of the positions can be determined as the center position ofgravity of the area over the threshold level 100 as shown in FIG. 13(c).

[0082] The positions are determined with the use of the threshold levelfor the purpose of obtaining higher reliable position information withthe use of an image of a bright-enough point. If there are nobright-enough points in the threshold level, an image of the brightestpoint in the image may be used. If a pattern is less bright as pattern Das shown in FIG. 13 (b) and the brightness around the position of thepattern to be searched for is below a threshold level 101, this patterncan be determined as a failed pattern and the next pattern is checked.

[0083] After all pattern positions are determined, a typical brightnessvalue of each pattern is calculated. This can be an average value ofbrightness of points over the threshold level ThL 101, or a valuedetermined by calculating the sun of brightness of these points anddividing it by a number of pixels 103.

[0084] Repetitive pitch p of a pattern used for calculating positionscan be indicated by an operator 128 in advance, or can automatically becalculated from the design data.

[0085] As is evident from above, the threshold level ThL 100 for imageprocessing is a threshold for detecting a point of a pattern inreliability, which can be determined, for example, by adding thebrightness of the groundwork 92 to the brightness of about 70 percentsof amplitude of a pattern 104. In contrast to this, the threshold levelThL 101 is used for determining the presence or absence of patterns,which can be determined, for example, by adding the brightness of thegroundwork to the brightness of 10 to 20 percents of amplitude of thepattern 104. FIG. 13 illustrates the case were a pattern is brighterthan the groundwork, which is shown in white color for easier tounderstand. Although patterns can be inversed depending on electronicoptical system parameters, application of the methods shown in FIG. 12and FIG. 13 to that case enables evaluation of the brightness of apattern.

[0086] In addition, the same effect can be expected as in the case ofusing the typical brightness value when evaluation of the brightness ofa pattern with the use of the number of pixels of brightness of a rangebeyond the threshold level as a parameter indicating the dimension ofthe pattern instead of a typical brightness value as shown in FIG. 13(c).

[0087] As shown in FIG. 14 (b), if a pattern density is high and theratio of the area occupied by patterns to the groundwork is high, thereis no need to measure the typical brightness value of each pattern.Similar effect is obtained by evaluating the average brightness valueover an entire image and variations. In this case, since calculationamount for image processing is smaller than that for the examplementioned above, faster inspection is possible.

[0088] Furthermore, if the resolution of an electronic optic system ishigh, it is observed that a pattern edge 105 outshines the patternbecause of so called a white edge effect. In this case, it would bepossible to calculate the typical brightness value as in the case ofFIG. 13. As is the case with the example of FIG. 13, evaluation usingthe brightness only within a pattern would also be possible with the useof the image around a pattern center 106 after calculation of patternpositions and by processing around the white edge parts through edgedetecting operation. When the white edge parts are very bright,background noise can be reduced through these operations and subtlevariations of the brightness within the pattern can be determined.

[0089] In this way, typical brightness values of repetitive patterns canbe calculated through image processing. However, for patterns onproducts, surface potentials when irradiated by electron beams vary andsignal amount of a secondary electron beam image to be obtained variesdepending on distribution of impurities in the substrate, the presenceor absence of p-n junctions in the substrate, and difference in methodsof interconnection to other regions of traces.

[0090] For example, on forming contact windows shown in FIG. 3 throughthe process of a device shown in FIG. 1, contact conditions between thecontact windows and underlying conductors formed in a unit cell forconnection to a trace are different among groups A, B and C shown inFIG. 16 (a). Therefore, image processing allowing for the difference ofbrightness of these patterns is required. For this purpose, a unit cellarea 110 is set as shown by a dotted line, the positions of patternswithin the unit cell area 110 are registered in advance. For example,the top left coordinates of the unit cell area 110 are set as an origin111 and the coordinates of each pattern 112 can be registered based onit. This registration may be done through mouse operation by an operatorwhile checking the image, or may be made from the design dataautomatically. All or same of these patterns with the coordinatesregistered can be used to perform evaluation by pattern type similar tothat in the case of FIG. 6.

[0091] To determine pattern positions, operations such as ordinarytemplate-matching may be used. As shown in FIG. 16 (a), for example, apattern of the unit cell area 110 that has been obtained in a normalsection is stored as a template image 113, a pattern 114 correspondingto the template image 113 is detected within a range of repetitive cellpattern pitch, and, subsequently, similar patterns are searched foraround the coordinates at a distant of a pattern pitch pp. At this time,if an obtained image and the pattern of the template image 113 have alow correlation value, the brightness within the obtained image isevaluated to determine the presence or absence of patterns. For example,if only the brightness of the same level as that of the groundworkexists, it can be determined that the peripheral area is faulty. If theposition of a unit cell can be determined, pattern positions within theunit cell can easily be determined on the basis of the coordinates thathave been registered in advance.

[0092] Since many other possible methods for identifying patternpositions and measuring typical values exist, an appropriate imageprocessing method can be used as the case may be.

[0093] Next, A method of determining the threshold level ThL 68 forevaluating the quality of a pattern in the inspection using thebrightness of a charged particle beam image of the invention will bedescribed. As another embodiment of the method (shown in FIG. 7) fordetermining the threshold level ThL 68 using the relationship betweenthe brightness measured in advance and resistance values, there is Amethod of determining the inspection threshold level at the time ofproposition of the production parameters.

[0094] Usually, when a new product is introduced into a production line,production parameters are proposed. For instance, in the case ofexposure apparatus, parameters including exposure time, focus offset,alignment with lower layers, and rotating amount are defined, then usedto expose patterns practically, and adjusted to the best parametersdepending on the result. For etching, processing conditions are set bychanging gas to be used and etching time.

[0095] At this time, in-depth checks are performed by using criticaldimension measurement SEM combined with visual checks for cross sectionsas required. A method of evaluating the image of a formed pattern atthis time and determining the evaluation value will be described. Forexample, if the sample image for proposition of production parametersgenerated by changing etching time is obtained and evaluated, and theresult of the quality evaluation is plotted with the evaluation, thegraph as shown in FIG. 17 is obtained. In this way, if the relationshipbetween the result of quality evaluation and the typical brightnessvalue can be obtained, the control value 68 corresponding to a typicalbrightness value can be determined. In the example shown in FIG. 17, apattern that has been evaluated as faulty is indicated with a triangularmark 115 and a pattern that has been evaluated as normal is indicatedwith a round mark 116. From the result of this quality evaluation andthe measuring result of a typical brightness value, a brightnesstolerance 69 of a normal pattern can be determined and the control valueused in FIG. 6 can be determined.

[0096]FIG. 17 shows an example of proposition of etching timeparameters. At the time of proposition of other process parameters,control values can be determined similarly if the image feature amountof a normal section and a failed section can be obtained.

[0097] Next, an example of another control setting method will bedescribed by referring to FIG. 18. In a production process ofsemiconductor devices, operation checks of completed devices areperformed before shipping. The control values for inspection can also bedetermined with the use of the result of quality evaluations at thistime. For example, an inspection image is obtained at a certain stagebefore being matched to the result of the fail-bit analysis for theresulting produced device. As shown in FIG. 18, distribution of thetypical brightness value of normal bits 117 is obtained, which can beused to determine the control value. In FIG. 18, failures occur at bithaving the same typical brightness value of a normal section, becausefailures might occur at stages other than the stage of interest.

[0098] Since the brightness control value 68 used in FIG. 6 variesaccording to irradiation parameters including the acceleration voltagesof electron beams and beam current, it is required to determine itseparately by inspection apparatus to be used. If mixed kinds ofpatterns exist as shown in FIG. 16, a plurality of control values shouldbe set for each pattern group in which each pattern within a unit cellis the same or has the same geometry and characteristics, or only acertain pattern within a unit cell or pattern groups with the samegeometry and characteristics should be evaluated.

[0099] Next, A method of implementing an inspection system 132 carryingout these inspections will be described. FIG. 19 shows an example of aninspection system of this invention. A mainframe of an inspectionapparatus 120 consists of an electron optics system 121 for building upSEM images, a detector 122 for detecting secondary electron images, andan X-Y stage 123 for holding specimens and enabling observation ofdesired positions. A column controller 124 can adjust parameters such asthe acceleration voltages and current of irradiating beams and focusingpositions to obtain excellent inspection images. A stage controller 125can shift the X-Y stage 123 to a desired position to perform inspectionimage processing for the images that have been detected by the detector122 at an image processing unit 126. These are controlled by an entirecontrol unit 127 and can perform inspection operations as shown in FIG.6.

[0100] The operator 128 can easily specify inspection areas and displaythe inspection results on a GUI display 129. The entire control unit 127provides a function for receiving a working history 130 of a wafer to beinspected (information about the fabricating equipment and working time)from a process control system 131 and analyzing the inspection results.The entire control unit 127 is also connected to a failure analysissystem 133 and can receive the test results of inspected wafers and theresults of their fail-bit analysis.

[0101] The following shows an example of A method of preparing aninspection recipe. First, an item to be inspected and process areselected and inspection parts within a wafer, shot, or chip are decided.At this time, if failure-prone parts for production equipment are known,they should be specified as areas to be inspected without fail. Next,electron bear images of normal sections are obtained in practice todetermine the pattern brightness of the normal sections and thebrightness of the groundwork. At this time, the repetitive pitch of thecell pattern and compound patterns as shown in FIG. 16 are set. Finally,the control value is determined by the methods mentioned above.

[0102] If a charged particle bean unit 134 has a function for obtainingimages at desired positions within a wafer as ordinary SEM and FIB, itwould be possible to implement applications with many kinds of chargedparticle beam units by connecting to an external interface 135 forsending image obtaining commands and transferring obtained images to animage processing unit 136 capable of processing images and displayingthe results.

[0103] Next, a feedback method from the results to the productionprocess of the invention will be described. Although it is easy todetermine a process in which a failure occurs if inspections are carriedout at completion of each process shown in FIG. 4, it is practicallydifficult to perform inspection at all the processes.

[0104] For example, suppose an inspection is perform only after resiststripping at process n and process n+1. It would be impossible todetermine at which stage, from cleaning stage at process n to resiststripping stage at process n+1, failures detected after resist strippingstage at process n+1 have occurred. In this case, if there is a functionfor displaying inspection results specific to commencement equipment atevery stage from the cleaning stage at process n to the resist strippingstage at process n+1, it would increase the possibility of obtaininginformation beneficial to the identification of the equipment causingthe failures.

[0105] For example, the relationship between the typical brightnessvalue and the time and date of commencement as shown in FIGS. 21 (a),(b), and (c) can be displayed for each commencement equipment at eachtime and date of commencement. (In FIG. 21, information about an itemoperated upon equipment A is plotted in (b), and information about anitem operated upon equipment B is plotted in (c). Comparing the data ofFIG. 21 (b) to the data of FIG. 21 (c) makes it clear that theperformance of equipment B has gradually been exacerbated. It isimpossible to recognize the fact from the data for items only put intothe inspected order as shown in FIG. 21 (a), and makes it easy toidentify equipment that caused the failures.

[0106]FIG. 21 shows a typical brightness value per lot for simplicity,but the number of the typical brightness values is not limited to one,and the horizontal axis may be set in a unit of wafer. For theinspection on a plurality of points within a wafer, the mean value andthe minimum value of the brightness or all inspection results may bedisplayed at the same time. This method enables inspections in shortertime, or a few minutes per wafer, in comparison with ordinary inspectionapparatus using electron microscope, so, if the frequency of spot checksis increased, further reliable results reflecting equipment conditionswill be obtained. If it is programmed in such a way that the time seriesdata of the inspection results as shown in FIGS. 21 (b) and (c) isautomatically accumulated and that alarm is given when the data fallsbelow a reference level or when it abruptly varies, it would be possibleto control process changes.

[0107] If distribution of failures within a wafer surface 142 as shownin FIG. 21 (c), as well as the distribution of failures within a shotare displayed, it would make it easier to assume problem equipment. Ingeneral, information of manufacturing equipment and working time iscontrolled on production lines and the data can be available whennecessary. If it is recognizable in advance that the typical brightnessvalue of a pattern is gradually going down as shown in an example ofFIG. 21 (c), it would be possible to prevent occurrence of failures bycarrying out maintenance of equipment parts previously. In examplesshown in FIG. 21, the vertical axis of each graph indicates the typicalbrightness value of patterns but may indicate the occurrence probabilityof failed patterns or normal patterns that has been estimated by amethod in FIG. 6.

[0108] The invention makes it possible to keep track of failureoccurrence conditions on an entire wafer of interest only by inspectingminimum area, thereby implementing fast inspection and enabling itsin-line usage. In addition, the invention makes it possible to preventmass occurrence of failures due to defective conditions of manufacturingequipment by controlling change in processes.

[0109] The invention may be embodied in other specific forms withoutdeparting from the spirit or essential characteristics thereof. Thepresent embodiment is therefore to be considered in all respects asillustrative and not restrictive, the scope of the invention beingindicated by the appended claims rather than by the foregoingdescription and all changes which care within the meaning and range ofequivalency of the claims are therefore intended to be embraced therein.

1. A method of inspecting a wafer, comprising the steps of: irradiatingand scanning a focused charged particle beam onto a surface of a waferon which patterns are formed through a semiconductor device fabricationprocess; obtaining a secondary charged particle image of a desired areaof said wafer by detecting secondary charged particles emitted from saidsurface of said wafer through the irradiating and scanning step;obtaining information about image feature amount of each pattern withinsaid desired area from said obtained secondary charged particle beamimage; comparing information about image feature amount obtained in thestep of obtaining information with a preset value; estimating, on thebasis of a result from the step of comparing, a quality of patternswhich have been formed around said desired area; and outputting aninformation of a result of said estimating.
 2. A method of inspecting awafer according to the claim 1, wherein an information of said imagefeature amount is obtained for each type of the pattern in the step ofobtaining information.
 3. A method of inspecting a wafer according tothe claim 1, wherein said information about said image feature amount isobtained by calculating image feature amount of said pattern type andcomputing the statistic of said calculated image feature amount.
 4. Amethod of inspecting a wafer according to the claim 3, wherein saidimage feature amount of said pattern type to be calculated is a meanvalue or a maximum value of signal amount in the pattern section.
 5. Amethod of inspecting a wafer according to the claim 1, wherein saidimage feature amount of said pattern type to be calculated is adimension of the pattern section.
 6. A method of inspecting a waferaccording to the claim 1, wherein said preset value is a threshold levelthat has been preset in association with a pattern type.
 7. A method ofinspecting a wafer according to the claim 1, comprising a step ofpredetermining a threshold level for evaluating the quality of imagefeature amount from said image feature amount and the result of productinspection after the completion of the fabrication process.
 8. A methodof inspecting a wafer according to the claim 1, comprising a step ofpredetermining a threshold level for evaluating the quality of imagefeature amount from said image feature amount and the measurement valueof contact resistance between a pattern section and an underlyingconductor.
 9. A method of inspecting a wafer according to the claim 1,comprising a step of feeding said output of said estimated result backto said semiconductor device fabricating line.
 10. A method ofinspecting a wafer, comprising the steps of: irradiating a focusedcharged particle beam onto a desired area of said wafer with a pluralityof chips of the same pattern on it; obtaining a charged particle beamimage of said desired area; inspecting said desired area from saidcharged particle beam image; performing estimation of failure occurrenceconditions of said chip from the inspection data of said desired areafor said plurality of chips on said wafer; determining a distribution ofsaid estimated failure occurrence conditions on said chip; andoutputting information about said determined distribution of saidestimated failure occurrence conditions over said wafer.
 11. A method ofinspecting a wafer according to the claim 10, further comprising a stepof performing said estimation of failure occurrence conditions on saidchip for almost all chips on said wafer.
 12. A method of inspecting awafer according to the claim 10, further comprising the step ofdisplaying a chip that has been estimated to have a failure on the wafermap as distinguished from other chips.
 13. A method of inspecting awafer according to the claim 10, further comprising the step ofinspecting said desired area through said charged particle beam imagewith the help of brightness information of said charged particle beamimage of said desired area.
 14. An apparatus for inspecting a wafer,comprising: a charged particle beams scanning irradiation means forperforming scanning irradiation of a focused charged particle beam ontosaid surface of a wafer with patterns formed on it; a secondary chargedparticle beam detection means for detecting secondary charged particlesemitted from said surface of said wafer by scanning irradiation of afocused charged particle beam onto said surface of said wafer with thehelp of said charged particle beams scanning irradiation means; an imageobtaining means for obtaining a charged particle beam image of saidwafer from detected signals of secondary charged particles that havebeen detected with the help of said secondary charged particle beamdetection means; an information obtaining means for obtaininginformation about image feature amount on said surface of said waferfrom the charged particle bean image of said wafer that has beenobtained with the help of said image obtaining means; a storage meansfor storing a threshold level; an estimation means for estimating thequality of a pattern that has been formed on the periphery of saiddesired area by comparing information about image feature amount thathas been obtained with the help of said information obtaining means; andan outputting means for outputting information about the quality of saidpattern that has been estimated with the help of said estimation means.15. An apparatus for inspecting a wafer according to the claim 14,wherein said information obtaining means obtains information about saidimage feature amount by calculating image feature amount of said patternand computing the statistic of said calculated image feature amount. 16.An apparatus for inspecting a wafer according to the claim 15, whereinsaid image feature amount is a mean value or a maximum value of thesignal amount of a charged particle beam image of the pattern section.17. An apparatus for inspecting a wafer according to the claim 14,wherein said wafer has a plurality of types of patterns on it and saidthreshold level is stored in association with said types of patterns.18. An apparatus for inspecting a wafer according to the claim 14,further comprising: a section result inputting means for inputting theresults of product inspection after the completion of the fabricationprocess, and a threshold level calculating means for determining athreshold level from image feature amount that has been calculated withthe help of said image signature amount calculating means and the resultinformation of a product inspection after the completion of thefabricating process that has been input to said inspection resultinputting means, wherein the threshold level that has been determinedwith the help of said threshold level calculating means is stored intosaid storage means.